ABB PCD232A 3BHE022293R0101 励磁控制模块

     系统的软件设计根据硬件结构的总体划分，也可以分为两大部分来描述。整个系统的运行如图2所示，FPGA和DSP各自的程序独立运行，通过中断信号完成数据的实时交互。FPGA向DSP方向的指令是通过FPGA发送一个EDMA请求，DSP通过响应EDMA请求，建立EDMA通道，开始从FIFO中进行预处理后数据的读取，DSP向FPGA传输数据时，通过向FPGA发送一个中断信号，让其从FIFO中把压缩后的图像数据读出来。

整个系统工作流程可以简单描述如下：系统上电后，首先DSP由flash实现自举，并运行引导程序，之后转入EDMA等待状态，FPGA初始化后等待外部图像采集命令，收到图像采集命令后开始进行图像采集，并对采集到的图像进行预处理，预处理后的图像经过FIFO缓冲，在存储一定量的数据之后，FPGA通过半满信号向DSP发送EDMA请求，等待DSP响应，DSP一旦收到来自FPGA的EDMA请求，立即建立EDMA通道，从FIFO中读取数据到L2存储器，存满一帧图像后DSP开始图像压缩，等待一幅图像压缩完成之后，DSP会向FPGA发送中断信号，FPGA在收到中断信号后开始从 FIFO中读取压缩后的图像数据。一帧数据读完后，判断编码信号是否有效，如果有效则按同样的规则对下一帧图像进行压缩，如果无效则通知DSP结束。

The software design of the system can also be described in two parts based on the overall division of the hardware structure. The entire system runs as shown in Figure 2, with FPGA and DSP programs running independently and completing real-time data exchange through interrupt signals. The instruction from FPGA to DSP is to send an EDMA request through FPGA. DSP responds to the EDMA request, establishes an EDMA channel, and starts reading preprocessed data from FIFO. When DSP transmits data to FPGA, it sends an interrupt signal to FPGA to read the compressed image data from FIFO.

The entire system workflow can be briefly described as follows: After the system is powered on, the DSP is first booted by flash and the boot program is run. Then, it enters the EDMA waiting state. After FPGA initialization, it waits for external image acquisition commands. After receiving the image acquisition commands, it starts image acquisition and preprocesses the collected images. The preprocessed images are buffered in FIFO and stored in a certain amount of data, The FPGA sends an EDMA request to the DSP through a half full signal, waiting for the DSP to respond. Once the DSP receives an EDMA request from the FPGA, it immediately establishes an EDMA channel and reads data from the FIFO into the L2 memory. After one frame of image is filled, the DSP starts image compression. After waiting for an image compression to be completed, the DSP sends an interrupt signal to the FPGA. After receiving the interrupt signal, the FPGA starts reading the compressed image data from the FIFO. After reading a frame of data, determine whether the encoded signal is valid. If it is valid, compress the next frame of image according to the same rules. If it is invalid, notify the DSP to end.

ABB 全系列高压模块 伺服控制器：PCD232A 3BHE022293R0101 励磁控制模块

GFD233A 3BHE022294R0103

FET3251C0P184C0H2

5SHY3545L0009

3BHB013085R0001

3BHE009681

5SHX08F4502

CP405 A0 1SAP500405R0001

PM866-2 3BSE050201R1

DI04

CAI04

PM866-23BSE050201R1

PU515A 3BSE032401R1

ICSE08B5 FPR3346501R1012

R474A11XE

REF615A_E

PM864AK01 3BSE018161R1

PCD232A 3BHE022293R01

REF542PLUS 1VCF752000

PPD113B03-26-100100

3BHE023584R2625

PP865A 3BSE042236R2

3ASC25H216A DATX132

3ASC25H208 DATX100

3ASC25H214 DATX130

3ASC25H204 DAPU100

3ASC25H219B DATX133

PPD512A10-150000

LWN2660-6

REF615E E

UNITR0L 1020 UNS0119A-Z,V1

3BHE030579R0003

C1570 3BSE001440R1

PP865A 3BSE042236R2

1MRK00008-KB